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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>SMLALL (multiple and indexed vector)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">SMLALL (multiple and indexed vector)</h2><p>Multi-vector signed integer multiply-add long-long by indexed element</p>
      <p class="aml">This signed integer multiply-add long-long instruction multiplies each signed 8-bit or 16-bit element in the one, two, or four first source vectors with each signed 8-bit or 16-bit indexed element of second source vector, widens each product to 32-bits or 64-bits and destructively adds these values to the corresponding 32-bit or 64-bit elements of the ZA quad-vector groups.</p>
      <p class="aml">The elements within the second source vector are specified using an immediate element index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 3 to 4 bits depending on the size of the element. The lowest of the four consecutive vector numbers forming the quad-vector group within all of, each half of, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.</p>
      <p class="aml">The <span class="arm-defined-word">vector group</span> symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The <span class="arm-defined-word">vector group</span> symbol is preferred for disassembly, but optional in assembler source code.</p>
      <p class="aml">This instruction is unpredicated.</p>
      <p class="aml">ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.</p>
    
    <p class="desc">
      It has encodings from 6 classes:
      <a href="#iclass_sme_mall_4words">One ZA quad-vector of 32-bit elements</a>
      , 
      <a href="#iclass_sme_mall_4dwords">One ZA quad-vector of 64-bit elements</a>
      , 
      <a href="#iclass_sme_mall_8words">Two ZA quad-vectors of 32-bit elements</a>
      , 
      <a href="#iclass_sme_mall_8dwords">Two ZA quad-vectors of 64-bit elements</a>
      , 
      <a href="#iclass_sme_mall_16words">Four ZA quad-vectors of 32-bit elements</a>
       and 
      <a href="#iclass_sme_mall_16dwords">Four ZA quad-vectors of 64-bit elements</a>
    </p>
    <h3 class="classheading"><a id="iclass_sme_mall_4words"/>One ZA quad-vector of 32-bit elements<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td colspan="4" class="lr">Zm</td><td class="lr">i4h</td><td colspan="2" class="lr">Rv</td><td colspan="3" class="lr">i4l</td><td colspan="5" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">off2</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td colspan="3"/><td colspan="5"/><td class="droppedname">U</td><td class="droppedname">S</td><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="smlall_za_zzi_s"/><p class="asm-code">SMLALL  ZA.S[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf" title="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;off2&quot; field times 4 (field off2)">&lt;offsf&gt;</a>:<a href="#sa_offsl" title="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;off2&quot; field times 4 plus 3 (field off2)">&lt;offsl&gt;</a>], <a href="#sa_zn" title="First source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.B, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.B[<a href="#sa_index_1" title="Element index [0-15] (field &quot;i4h:i4l&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
constant integer esize = 32;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off2:'00');
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i4h:i4l);
constant integer nreg = 1;</p>
    <h3 class="classheading"><a id="iclass_sme_mall_4dwords"/>One ZA quad-vector of 64-bit elements<span style="font-size:smaller;"><br/>(FEAT_SME_I16I64)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td colspan="4" class="lr">Zm</td><td class="lr">i3h</td><td colspan="2" class="lr">Rv</td><td class="lr">0</td><td colspan="2" class="lr">i3l</td><td colspan="5" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">off2</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td/><td colspan="2"/><td colspan="5"/><td class="droppedname">U</td><td class="droppedname">S</td><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="smlall_za_zzi_d"/><p class="asm-code">SMLALL  ZA.D[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf" title="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;off2&quot; field times 4 (field off2)">&lt;offsf&gt;</a>:<a href="#sa_offsl" title="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;off2&quot; field times 4 plus 3 (field off2)">&lt;offsl&gt;</a>], <a href="#sa_zn" title="First source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.H, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.H[<a href="#sa_index" title="Element index [0-7] (field &quot;i3h:i3l&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !(<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() &amp;&amp; <a href="shared_pseudocode.html#impl-aarch64.HaveSMEI16I64.0" title="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>()) then UNDEFINED;
constant integer esize = 64;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off2:'00');
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i3h:i3l);
constant integer nreg = 1;</p>
    <h3 class="classheading"><a id="iclass_sme_mall_8words"/>Two ZA quad-vectors of 32-bit elements<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td colspan="4" class="lr">Zm</td><td class="lr">0</td><td colspan="2" class="lr">Rv</td><td class="lr">0</td><td colspan="2" class="lr">i4h</td><td colspan="4" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">i4l</td><td class="lr">o1</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td/><td colspan="2"/><td colspan="4"/><td/><td class="droppedname">U</td><td class="droppedname">S</td><td colspan="2"/><td/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="smlall_za_zzi_s2xi"/><p class="asm-code">SMLALL  ZA.S[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf_1" title="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a>{, VGx2}], { <a href="#sa_zn1" title="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a>.B-<a href="#sa_zn2" title="Second scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn2&gt;</a>.B }, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.B[<a href="#sa_index_1" title="Element index [0-15] (field &quot;i4h:i4l&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
constant integer esize = 32;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn:'0');
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i4h:i4l);
constant integer nreg = 2;</p>
    <h3 class="classheading"><a id="iclass_sme_mall_8dwords"/>Two ZA quad-vectors of 64-bit elements<span style="font-size:smaller;"><br/>(FEAT_SME_I16I64)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">1</td><td colspan="4" class="lr">Zm</td><td class="lr">0</td><td colspan="2" class="lr">Rv</td><td class="l">0</td><td class="r">0</td><td class="lr">i3h</td><td colspan="4" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">i3l</td><td class="lr">o1</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td colspan="2"/><td/><td colspan="4"/><td/><td class="droppedname">U</td><td class="droppedname">S</td><td colspan="2"/><td/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="smlall_za_zzi_d2xi"/><p class="asm-code">SMLALL  ZA.D[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf_1" title="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a>{, VGx2}], { <a href="#sa_zn1" title="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a>.H-<a href="#sa_zn2" title="Second scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn2&gt;</a>.H }, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.H[<a href="#sa_index" title="Element index [0-7] (field &quot;i3h:i3l&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !(<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() &amp;&amp; <a href="shared_pseudocode.html#impl-aarch64.HaveSMEI16I64.0" title="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>()) then UNDEFINED;
constant integer esize = 64;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn:'0');
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i3h:i3l);
constant integer nreg = 2;</p>
    <h3 class="classheading"><a id="iclass_sme_mall_16words"/>Four ZA quad-vectors of 32-bit elements<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td colspan="4" class="lr">Zm</td><td class="lr">1</td><td colspan="2" class="lr">Rv</td><td class="lr">0</td><td colspan="2" class="lr">i4h</td><td colspan="3" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">i4l</td><td class="lr">o1</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td/><td colspan="2"/><td colspan="3"/><td/><td/><td class="droppedname">U</td><td class="droppedname">S</td><td colspan="2"/><td/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="smlall_za_zzi_s4xi"/><p class="asm-code">SMLALL  ZA.S[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf_1" title="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a>{, VGx4}], { <a href="#sa_zn1_1" title="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a>.B-<a href="#sa_zn4" title="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a>.B }, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.B[<a href="#sa_index_1" title="Element index [0-15] (field &quot;i4h:i4l&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
constant integer esize = 32;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i4h:i4l);
constant integer nreg = 4;</p>
    <h3 class="classheading"><a id="iclass_sme_mall_16dwords"/>Four ZA quad-vectors of 64-bit elements<span style="font-size:smaller;"><br/>(FEAT_SME_I16I64)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">1</td><td colspan="4" class="lr">Zm</td><td class="lr">1</td><td colspan="2" class="lr">Rv</td><td class="l">0</td><td class="r">0</td><td class="lr">i3h</td><td colspan="3" class="lr">Zn</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">i3l</td><td class="lr">o1</td></tr><tr class="secondrow"><td colspan="12"/><td colspan="4"/><td/><td colspan="2"/><td colspan="2"/><td/><td colspan="3"/><td colspan="2"/><td class="droppedname">U</td><td class="droppedname">S</td><td colspan="2"/><td/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="smlall_za_zzi_d4xi"/><p class="asm-code">SMLALL  ZA.D[<a href="#sa_wv" title="32-bit vector select register W8-W11 (field &quot;Rv&quot;)">&lt;Wv&gt;</a>, <a href="#sa_offsf_1" title="Vector select offset, pointing to first of four consecutive vectors, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Vector select offset, pointing to last of four consecutive vectors, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a>{, VGx4}], { <a href="#sa_zn1_1" title="First scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn1&gt;</a>.H-<a href="#sa_zn4" title="Fourth scalable vector register of a multi-vector sequence (field Zn)">&lt;Zn4&gt;</a>.H }, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field &quot;Zm&quot;)">&lt;Zm&gt;</a>.H[<a href="#sa_index" title="Element index [0-7] (field &quot;i3h:i3l&quot;)">&lt;index&gt;</a>]</p></div><p class="pseudocode">if !(<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() &amp;&amp; <a href="shared_pseudocode.html#impl-aarch64.HaveSMEI16I64.0" title="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>()) then UNDEFINED;
constant integer esize = 64;
integer v = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i3h:i3l);
constant integer nreg = 4;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wv&gt;</td><td><a id="sa_wv"/>
        
          <p class="aml">Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offsf&gt;</td><td><a id="sa_offsf"/>
        
          <p class="aml">For the one ZA quad-vector of 32-bit elements and one ZA quad-vector of 64-bit elements variant: is the vector select offset, pointing to first of four consecutive vectors, encoded as "off2" field times 4.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsf_1"/>
        
          <p class="aml">For the four ZA quad-vectors of 32-bit elements, four ZA quad-vectors of 64-bit elements, two ZA quad-vectors of 32-bit elements and two ZA quad-vectors of 64-bit elements variant: is the vector select offset, pointing to first of four consecutive vectors, encoded as "o1" field times 4.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offsl&gt;</td><td><a id="sa_offsl"/>
        
          <p class="aml">For the one ZA quad-vector of 32-bit elements and one ZA quad-vector of 64-bit elements variant: is the vector select offset, pointing to last of four consecutive vectors, encoded as "off2" field times 4 plus 3.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsl_1"/>
        
          <p class="aml">For the four ZA quad-vectors of 32-bit elements, four ZA quad-vectors of 64-bit elements, two ZA quad-vectors of 32-bit elements and two ZA quad-vectors of 64-bit elements variant: is the vector select offset, pointing to last of four consecutive vectors, encoded as "o1" field times 4 plus 3.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn&gt;</td><td><a id="sa_zn"/>
        
          <p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn1&gt;</td><td><a id="sa_zn1"/>
        
          <p class="aml">For the two ZA quad-vectors of 32-bit elements and two ZA quad-vectors of 64-bit elements variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.</p>
        
      </td></tr><tr><td/><td><a id="sa_zn1_1"/>
        
          <p class="aml">For the four ZA quad-vectors of 32-bit elements and four ZA quad-vectors of 64-bit elements variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn4&gt;</td><td><a id="sa_zn4"/>
        
          <p class="aml">Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn2&gt;</td><td><a id="sa_zn2"/>
        
          <p class="aml">Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zm&gt;</td><td><a id="sa_zm"/>
        
          <p class="aml">Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;index&gt;</td><td><a id="sa_index_1"/>
        
          <p class="aml">For the four ZA quad-vectors of 32-bit elements, one ZA quad-vector of 32-bit elements and two ZA quad-vectors of 32-bit elements variant: is the element index, in the range 0 to 15, encoded in the "i4h:i4l" fields.</p>
        
      </td></tr><tr><td/><td><a id="sa_index"/>
        
          <p class="aml">For the four ZA quad-vectors of 64-bit elements, one ZA quad-vector of 64-bit elements and two ZA quad-vectors of 64-bit elements variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
constant integer elements = VL DIV esize;
integer vectors = VL DIV 8;
integer vstride = vectors DIV nreg;
integer eltspersegment = 128 DIV esize;
bits(32) vbase = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
integer vec = (<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
bits(VL) result;
vec = vec - (vec MOD 4);

for r = 0 to nreg-1
    bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+r, VL];
    bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
    for i = 0 to 3
        bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.ZAvector.read.2" title="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec + i, VL];
        for e = 0 to elements-1
            integer segmentbase = e - (e MOD eltspersegment);
            integer s = 4 * segmentbase + index;
            integer element1 = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);
            integer element2 = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, s, esize DIV 4]);
            bits(esize) product = (element1 * element2)&lt;esize-1:0&gt;;
            <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize] + product;
        <a href="shared_pseudocode.html#impl-aarch64.ZAvector.write.2" title="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec + i, VL] = result;
    vec = vec + vstride;</p>
    </div>
  <h3>Operational information</h3><p class="aml">If PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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